The present invention relates to a semiconductor device and a method of manufacturing same.
Semiconductor devices equipped with an insulated gate field effect transistor portion such as power MOSFET (metal oxide semiconductor field effect transistor) and a snubber portion are known (refer to Patent Documents 1 and 2). When then insulated gate field effect transistor portion is used as a high-speed switching element, a surge voltage may occur between a source electrode and a drain electrode at turn-off. The surge voltage exceeding the withstand voltage of the insulated gate field effect transistor portion destroys the insulated gate field effect transistor portion. A snubber circuit between the source electrode and the drain electrode can reduce this surge voltage and thereby suppress the insulated gate field effect transistor portion from being destroyed.
A capacitor in a snubber portion of a semiconductor device disclosed in Patent Document 1 includes an n− type epitaxial layer, a trench source electrode, and a capacitive insulating film between the n− type epitaxial layer and the trench source electrode. The n− type epitaxial layer is coupled to a drain electrode. The capacitive insulating film and the trench source electrode are provided in a trench formed in the n− type epitaxial layer.
A capacitor in a snubber portion of a semiconductor device disclosed in Patent Document 2 includes an n− type drift layer, a p type body layer on the n− type drift layer, a snubber electrode, and an insulating film between the n− type drift layer and the snubber electrode. The n− type drift layer is coupled to a drain electrode. The n− type drift layer functions as a drift layer in an insulated gate field effect transistor portion. The insulating film and the snubber electrode are provided in a trench formed in the n− type drift layer and the p type body layer.